| JStamp and common logic family voltage
levels |
| JStamp I/O pins are 3.3V TTL-level,
and are 5V tolerant. They will interface to other standard TTL-level
devices, regardless of whether those devices are themselves powered
by 3V or 5V. "TTL-level" means that the voltages which will
be interpreted as a "low" or "high" level are
anything less than 0.8 volts, or more than 2.0 volts, respectively.
There are a confusing variety of component families available, mostly
due to the technology push to reduce power consumption. Any device
with a "T" in its prefix (e.g., 74HCT574, 74ACT574, 75FCT574)
is TTL compatible as are all "LS" devices (e.g. 74LS374).
"HC" or "AC" devices are CMOS-, not TTL- level
devices. It's always good advice (and will save you time in the long
run) to carefully read the data sheets of any chips or devices you
will connect to JStamp. Most I/O devices are TTL level, but occasionally
you find some non-conforming ones. |
| JStamp input thresholds |
Vil is 0.8V max, Vih is 2.0V min.
Note that this is incorrectly stated in the aJ-100 technical reference
as 1.0 and 2.3. The correct values are TTL thresholds of 0.8 and 2.0
volts. |
| JStamp output levels |
Vol is 0.4V max and Voh is 2.4V min.
These are for an output loaded to its maximum specified load. GPIOA
sink and source up to 24 mA, other GPIOs sink and source 8 mA. At
lighter loads, Vol will be lower (closer to 0.0) and Voh will be higher
(closer to 3.3V).
JStamp is powered internally by a 3.3V regulator and a smaller
2.5V regulator for the aJ80 core. So 3.3V is the
only supply voltage available to power JStamp I/O pins. This limits
the output voltage of JStamp pins to 3.3 volts, unless they are connected
to external sources at a higher voltage (such as the MAX232 serial
level shifter used on the JStamp development station, which can drive
the JStamp serial I/O pins to 5V TTL levels). |
| TTL input thresholds |
Vil=0.8V max and Vih=2.0V max. These
thresholds are valid regardless of the supply voltage if the part
is specified as "TTL level compatible" |
| TTL output levels |
Vol is 0.4V max and Voh is 2.4V min.
These are for an output loaded to its maximum specified load. At
lighter
loads, Vol will be lower (closer to 0.0) and Voh will be higher (closer
to Vcc of 3.3).
If you connect JStamp pins to external 5-volt logic, you may see
the voltage on those pins swing up to 5 volts. This is normal -
any such higher voltages on a JStamp pin can only be provided by
external logic - JStamp cannot drive it's own pins higher than 3.3V
since 3.3V is the only voltage supply available to the aJ80 controller. |
| HC input thresholds |
CMOS devices switch at
Vcc/2 typical which is 1.65V at Vcc = 3.3. |
| CMOS devices switch at Vcc/2 typical,
which is 2.5V for 5V Vcc. At 4.5V Vcc, Vil max is 1.35V and Vih max
is 3.15V. |
| LS input thresholds |
Same as TTL: Vil is 0.8V max, Vih
is 2.0V max. |
| HCT input thresholds |
Same as TTL: Vil is 0.8V max, Vih
is 2.0V max. |
| Interfacing JStamp to common logic
families |
| JStamp I/O pins are 3.3V
TTL-level, and are 5V tolerant. This simple statement defines how
they interface to other logic families. Here's a table of the common
possibilities. |
|
Logic family
|
Interface considerations to JStamp
|
| 5V TTL devices (74HCT,
74ACT, 74LS, 74S, 74F, etc) |
Connect directly. Fully
compatible with either JStamp or 5.0V TTL devices as the input or
output. |
| 3V CMOS (newer families
such as LCX or LVX) |
Connect directly. Fully
compatible with either JStamp or 3.3V CMOS devices as the input or
output. Read the data sheet to be sure as some older CMOS devices
are vague about exact performance at 3.3V |
| 5V CMOS output to JStamp
input |
Compatible, since the
CMOS output will swing below 1V and above 2.3V and keep the JStamp
input satisfied. |
| JStamp output to 5V CMOS input |
Won't work reliably since 5V CMOS
needs Vih of as much as 3.15V and JStamp provides 2.4V min. JStamp
actually will provide closer to 3.3V with a very light load but don't
count on that. Use a level shifter or buffer. There are special buffers
made for this - for example "4245" family such as Philips74LVC4245A
or Fairchild 74LVX4245. |
| JStamp Pinouts |
|
Pin # |
Signal Name |
I/O |
Description |
| 1
|
+3.3V |
I/O |
If you power JStamp
through its VRAW input (pin 40) JStamp's power converter provides
3.3V @ 100 mA on this pin for your use off-module. You can alternatively
provide JStamp with regulated 3.3 VDC +/- 5% on this pin and not provide
power on the VRAW input. |
| 2
|
GND |
|
System ground |
| 3
|
IOA4 |
I/O |
Bit programmable I/O
signal and external interrupt input. 24 mA sink/source |
| 4
|
IOA3 |
I/O |
Bit programmable I/O
signal and external interrupt input. 24 mA sink/source |
| 5
|
IOA2 |
I/O |
Bit programmable I/O
signal and external interrupt input. 24 mA sink/source |
| 6
|
IOA1 |
I/O |
Bit programmable I/O
signal and external interrupt input. 24 mA sink/source |
| 7
|
IOA0 |
I/O |
Bit programmable I/O
signal and external interrupt input. 24 mA sink/source Also drives
the JStamp heartbeat and status LED through a PNP transistor (so that
it doesn't load down this pin). |
| 8
|
GND |
|
System ground |
| 9
|
CLK0 |
O |
aJ-80 Clkout signal,
a programmable divider output. Derived from the internal processor
clock divided by 2, 4, or 8. The clock output may also be disabled
when an external clock is not necessary. |
| 10
|
GND |
|
System ground |
| 11
|
IOB5 |
I/O |
8 mA sink/source I/O
pin |
| 12
|
IOB4 |
I/O |
8 mA sink/source I/O
pin |
| 13
|
IOC6 |
I/O |
8 mA sink/source I/O
pin. Also SPI Transfer Clock. |
| 14
|
IOC5/FA1 |
I/O |
8 mA sink/source I/O
pin. Also SPI Master In/Slave Out. (Also used
by JStamp during flash programming - so be careful to not drive this
pin externally during flash programming operations). |
| 15
|
IOC4/FA0 |
I/O |
8 mA sink/source I/O
pin. Also SPI Master Out/Slave In. When operating in master mode MOSI
is an output used to transmit data to the slave device. When operating
in the slave mode MISO is input which receives data from the slave
device. (Also used by JStamp during flash programming
- so be careful to not drive this pin externally during flash programming
operations). |
| 16
|
IOC3 |
I/O |
8 mA sink/source I/O
pin, Also SPI Slave Chip Select 3. |
| 17
|
IOC1 |
I/O |
8 mA sink/source I/O
pin. Also SPI Slave Chip Select 1. |
| 18
|
IOC0 |
I/O |
8 mA sink/source I/O
pin. Also SPI Slave Chip Select 0/Slave Mode Select. |
| 19
|
IOD6 |
I/O |
8 mA sink/source I/O
pin |
| 20
|
GND |
|
System ground |
| 21
|
GND |
|
System ground |
| 22
|
IOD5/RXDA |
I/O |
8 mA sink/source I/O
pin, also UARTA RXD - more RS-232 info |
| 23
|
IOD4/TXDA |
I/O |
8 mA sink/source I/O
pin, also UARTA TXD - more RS-232 info |
| 24
|
IOD1/RXDB |
I/O |
8 mA sink/source I/O
pin, also UARTB RXD - more RS-232 info |
| 25
|
IOD0/TXDB |
I/O |
8 mA sink/source I/O
pin, also UARTB TXD - more RS-232 info |
| 26
|
IOE7 |
I/O |
8 mA sink/source I/O
pin |
| 27
|
IOE6 |
I/O |
8 mA sink/source I/O
pin |
| 28
|
IOE4 |
I/O |
8 mA sink/source I/O
pin |
| 29
|
IOE3 |
I/O |
8 mA sink/source I/O
pin |
| 30
|
GND |
|
System ground |
| 31
|
SWAP_MEM(L) |
I |
This pin has a pullup
resistor. If left floating high, Flash memory is located at location
0, the boot vector. If pulled to ground, SRAM will be at the boot
location 0. This pin will typically be pulled low to use SRAM for
your code during development, then allowed to float high once your
application is deployed in flash. |
| 32
|
JTAG_TDO |
O |
JTAG Test Data Output,
see note 2 |
| 33
|
JTAG_TDI |
I |
JTAG Test Data Input,
see note 2 |
| 34
|
JTAG_TMS |
I |
JTAG Test Mode Select.
The TMS input controls sequencing through the 1149 test access port
(TAP) state machine. see note 2 |
| 35
|
JTAG_TCK |
I |
JTAG Test Clock input,
see note 2 |
| 36
|
CRST(L) |
I/O |
Open-drain reset to/from
JStamp's reset controller and the aJ-80. JStamp circuitry drives this
pin low whenever voltage at the JStamp is below acceptable levels.
This pin can also be driven by the JTAG debugger interface. JStamp
has a 10K pullup to 3.3V on this pin. You may connect it to other
logic in your system which you want to be reset by JStamp. Connect
only to other open-drain or open-collector devices or to inputs of
your system. (Do not drive this signal with a totem-pole output from
your system or you will prevent JStamp from functioning properly.)
You can drive this with an open-drain or open-collector output from
your system to cause JStamp to reset (you can also use the RESET_PB
input). |
| 37
|
N/C |
|
Not connected or used.
Do not connect anything to this pin. May be used in a future JStamp
revision. |
| 38
|
RESET_PB(L) |
I |
Input from a reset pushbutton.
Circuitry on JStamp debounces this input. Use to reset JStamp. |
| 39
|
GND |
|
System ground |
| 40
|
VRAW |
I |
Raw power input, 5-14
VDC (4.75V min), unregulated. JStamp itself draws 30-80 mA at 5V (dependent
on processor speed which is controlled by your firmware). At 7.3728
MHz, JStamp draws about 10 mA from a 9V battery. |
| Notes
on JStamp GPIO (General Purpose I/O) |
| 1
|
JStamp GPIO pins are 3.3V max Voh, compatible with
TTL levels, and are 5V I/O tolerant. They interface with no additional
circuitry to 3.3V and 5V TTL-level devices.
|
| 2 |
JTAG pins must be connected only to a Systronix
JTAG adapter or Xilinx Parallel III programming adapter. Any other
connection voids your warranty and may damage JStamp.
|
| 3 |
JStamp grounds are all connected together, so in
a minimal system you only need to connect at least one to your system.
More is better, so connect them all if possible.
|
| 4 |
Each GPIO pin may be individually configured as
input or an output. Every GPIO pin may also be configured to generate
a CPU interrupt. Interrupt flexibility is provided by allowing interrupts
to be triggered on a rising edge, falling edge, either edge, high
level, or low level. To minimize pin-count most of the GPIO signals
are multiplexed with other I/O signals of the aJ-80. On a reset
the multiplexed signals are configured as GPIO inputs. Operation
of the multiplexed signals is controlled with the I/O configuration
registers.
|
| 5 |
JStamp assigns some GPIO pins to specific purposes
when using the JSimm interface. |
